Abstract
This paper presents performance of Quasi-Cyclic low-density parity-check (QC-LDPC) codes on a flat Rayleigh fading channels by employing DPSK modulation scheme. The BER curves show that large girth and diversity level robust the system performance. Moreover, Prototype architecture of the LDPC codes has been implemented by writing Hardware Description Language (VHDL) code and targeted to a Xilinx Spartan-3E XC3S500E FPGA chip. Simulation results show that the proposed QC-LDPC codes achieve a 0.1dB coding gain over randomly constructed codes and perform 1.3 dB from the Shannon-limit at a BER of 10-6 with a code rate of 0.89 for block length of 1332.
Original language | English |
---|---|
Title of host publication | ISCI 2011 - 2011 IEEE Symposium on Computers and Informatics |
Pages | 206-210 |
Number of pages | 5 |
DOIs | |
Publication status | Published - 2011 |
Event | 2011 IEEE Symposium on Computers and Informatics, ISCI 2011 - Kuala Lumpur, Malaysia Duration: Mar 20 2011 → Mar 22 2011 |
Other
Other | 2011 IEEE Symposium on Computers and Informatics, ISCI 2011 |
---|---|
Country/Territory | Malaysia |
City | Kuala Lumpur |
Period | 3/20/11 → 3/22/11 |
All Science Journal Classification (ASJC) codes
- Computer Networks and Communications
- Information Systems