TY - GEN
T1 - New QC-LDPC codes implementation on FPGA platform in Rayleigh fading environment
AU - Ghani, Farid
AU - Yahya, Abid
AU - Kader, Abdul
PY - 2011
Y1 - 2011
N2 - This paper presents performance of Quasi-Cyclic low-density parity-check (QC-LDPC) codes on a flat Rayleigh fading channels by employing DPSK modulation scheme. The BER curves show that large girth and diversity level robust the system performance. Moreover, Prototype architecture of the LDPC codes has been implemented by writing Hardware Description Language (VHDL) code and targeted to a Xilinx Spartan-3E XC3S500E FPGA chip. Simulation results show that the proposed QC-LDPC codes achieve a 0.1dB coding gain over randomly constructed codes and perform 1.3 dB from the Shannon-limit at a BER of 10-6 with a code rate of 0.89 for block length of 1332.
AB - This paper presents performance of Quasi-Cyclic low-density parity-check (QC-LDPC) codes on a flat Rayleigh fading channels by employing DPSK modulation scheme. The BER curves show that large girth and diversity level robust the system performance. Moreover, Prototype architecture of the LDPC codes has been implemented by writing Hardware Description Language (VHDL) code and targeted to a Xilinx Spartan-3E XC3S500E FPGA chip. Simulation results show that the proposed QC-LDPC codes achieve a 0.1dB coding gain over randomly constructed codes and perform 1.3 dB from the Shannon-limit at a BER of 10-6 with a code rate of 0.89 for block length of 1332.
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U2 - 10.1109/ISCI.2011.5958912
DO - 10.1109/ISCI.2011.5958912
M3 - Conference contribution
AN - SCOPUS:80052124100
SN - 9781612846903
T3 - ISCI 2011 - 2011 IEEE Symposium on Computers and Informatics
SP - 206
EP - 210
BT - ISCI 2011 - 2011 IEEE Symposium on Computers and Informatics
T2 - 2011 IEEE Symposium on Computers and Informatics, ISCI 2011
Y2 - 20 March 2011 through 22 March 2011
ER -